Configurable semiconductor devices allow chip designers to configure input/output devices (hereinafter, I/Os) during metallisation or programming steps. Examples of configurable semiconductor devices include rapid chips and field programmable devices. A rapid chip is a fixed and pre-diffused semiconductor device, which is later metalized in different configurations according to a specific application and according to user requirements. Limited layers may also be fixed. A field programmable device is a semiconductor device having logic blocks of gate arrays. Field programmable devices, which may also be pre-diffused, are configured with software or metalized to perform various functions according to a specific application and according to user requirements.
Before a pre-diffused semiconductor device is metalized with metal traces or wire bonds, it is referred to as a “slice.” Certain metal layers may also be fixed in the slice. After a slice is metalized, it is referred to as an “instance.”
Configurable semiconductor devices provide silicon re-usability across many different applications, using configurable I/Os, which can be configured during the creation of an instance to perform different functions and to operate at different operating voltages that may be required by each distinct application.
Semiconductor devices are implemented with various types of packages such as wirebond packages and flip chip packages, both of which are described below. FIG. 1 is a diagram of a conventional wirebond package 100. The wirebond package 100 includes an integrated circuit (IC) die (hereinafter, die 102), core logic 104, I/O segments 110, I/Os 112, pad wires 114, bond pads 116, signal fingers 120, power connections 130, and power planes 140.
During a configuration operation, the I/Os 112 are configured to interface the core logic 104 with the environment external to the wirebond package 100. Examples of external environments include application-specific standard product (ASSP) environment or an application-specific integrated circuit (ASIC). The pad wires 114 and bond pads 116 connect the I/Os 112 to the signal fingers 120, and to the power planes 140. The signal fingers 120 connect the I/Os 112 to signals or to discrete power in the external environment.
The I/Os 112 are also configured to operate at certain operating voltages (e.g. 1.2V, 1.5V, 2.5V, and 3.3V) by being connected via a metal trace or bond wire 114 to one of the power planes 140 depending on the required voltage.
Each power plane 140 is dedicated to supplying a unique operating voltage to a particular I/O segment 110. The I/O segments 110 are typically located around the die perimeter, and each I/O segment 110 is connected to the power plane 140 that is the closest in proximity. This simplifies the routing of the wire bonds 114. Also, the lengths of the wire bonds 114 should be minimized to reduce power noise.
The number of I/O segments 110 corresponds to the number of power planes 140, which is typically the same number of potentially required operating voltages. For example, if there are potentially four operating voltages required, there will be four available power planes 140. Accordingly, the I/Os 112 will be partitioned into four I/O segments 110.
The I/O segments 110 each have the same number of I/Os 112, because it is unknown how many I/Os 112 will be required by a particular application to operate at a particular voltage. Accordingly, the maximum number of available I/Os 112 that could be configured for a given operating voltage is a direct function of the number of power planes 140 in the wirebond package 100. If the total number of I/Os 112 is evenly allocated to the existing I/O segments 110, there should be, in principle, a sufficient number of I/Os 112 that can be configured for a given voltage requirement.
A problem with this conventional solution is that there is a pre-defined number of I/Os 112 per I/O segment 110. Consequently, this limits the number of I/Os 112 that can be supplied with a unique operating voltage. Consider the following example. A total of 44 configurable I/Os 112 exist on the die 102. However, the number of available voltages is limited by the number of power planes 140. Since there are only four power planes 140, there are only four available voltages. Accordingly, 11 I/Os may be configured for a voltage A, 11 I/Os may be configured for a voltage B, 11 I/Os may be configured for voltage C, and 11 I/Os may be configured for a voltage D.
Assume a particular application requires 44 I/O signals. In principle, the wirebond package 100 should suffice. However, the application may require more I/Os 112 than are available in a given I/O segment 110 of the wirebond package 100. For example, 9 I/Os may require voltage A, 14 I/Os may require voltage B, 6 I/Os may require voltage C, and 15 I/Os may require voltage D. Accordingly, the wirebond package 100 would not suffice. To suitably meet these constraints, a different wirebond package slice must be chosen. Such a slice will require a larger population of configurable I/Os (i.e. at least 15 available I/Os per voltage plane). Additionally, a larger package and package body size will be necessary as a result of using the larger-populated slice. Consequently, this increases the cost of the die and the package, and increases the package body size, which will have to be accommodated for at the system level.
Another problem with the conventional solution is that if only some of the I/Os 112 in a given I/O segment 110 is required for a given operating voltage, the remaining unused I/Os 112 in that I/O segment 110 becomes wasted. Consequently, instance designers are not able to fully benefit from the configurable nature the I/Os 112.
Yet another problem with the conventional solution is that the effective locations of the I/Os 112 that must operate at a particular voltage are fixed to a particular I/O segment 110. Consequently, signals routed on a circuit board using the wirebond package 100 are forced to connect to specific I/O segments 110. This significantly restriction a board layout in terms of the configurable devices interacting with other semiconductor devices on or off the board. This also requires an extensive co-design effort to ensure that the I/O segments 110 on the die 102 are aligned with the power planes 140.
Yet another problem is that the number of power planes 140 that can be designed into the wirebond package 100 is limited due to space. Since there are a finite number of power planes 140, the number of I/O segments 110 is limited, and thus the number of I/Os 112 that can be configured for a particular operating voltage is limited.
FIG. 2 is a diagram of a conventional flipchip package 200. The flipchip package 200 includes a die 202, I/O segments 210, I/Os 212, metal traces 214, signal bumps 220, power connections 230, power planes 240, and power bumps 250. During a configuration operation, the I/Os 212 are configured to interface core logic (not shown) with the environment external to the flipchip package 200. The signal bumps 220 connect the I/Os 212 to signals or to discrete power in the external environment.
The I/Os 212 are also configured to operate at certain operating voltages by being connected via the metal traces 214 to one of the power planes 240 depending on the required voltage. Each power plane 240 is dedicated to supplying a unique operating voltage to a particular I/O segment 210. The I/O segments 210 are typically located around the die perimeter, and each I/O segment 210 is connected to the power plane 240 that is the closest in proximity.
The number of I/O segments 210 corresponds to the number of power planes 240, which is typically the same number of potentially required operating voltages. The I/O segments 210 each have the same number of I/Os 212, because it is unknown how many I/Os 212 will be required by a particular application to operate at a particular voltage. Accordingly, the maximum number of available I/Os 212 that could be configured for a given operating voltage is a direct function of the number of power planes 240 in the flipchip package 200.
With an understanding of the problems associated with the wirebond package 100 of FIG. 1, it can be seen that the flipchip package 200 of FIG. 2 has similar problems. One problem with this conventional solution is that the number of I/Os 212 that can be supplied with a unique voltage is limited. Another problem is that if only some of the I/Os 212 in a given I/O segment 210 is required for a given operating voltage, the remaining unused I/Os 212 in that I/O segment 210 become wasted. Another problem is that the effective locations of the I/Os 212 that must operate at a particular voltage are fixed to a particular I/O segment 210, thus restricting a board layout. Finally, the number of power planes 240 in the flipchip package 200 is limited.
Generally, there is not a good solution to this problem today in that the known solutions have reduced flexibility in how I/Os can be configured for functionality and for power. To increase flexibility, a user must choose a package having more I/Os and voltage planes. Alternatively, the user must opt for a more expensive ASIC-based solution. These alternatives increase manufacturing costs.
Accordingly, what is needed is an improved system for implementing a configurable semiconductor device. The system should be flexible, optimal, simple, cost effective, and capable of being easily adapted to existing technology. The present invention addresses such a need.